Companies That Produce Asic Eda Tools For Digital System Design

This morning I attended Mentor Graphics's webinar about FPGA Synthesis, by Roger Do and Robert Jeffery.

Synthesis is a stage in the design flow that I personally give a lot of attention to the reports and the constraints. I am always excited about Synthesis. It is a moment that the designer and the synthesis tool share a bond. The webinar was fine and the key items covered were

Register retiming
Resource sharing
Physical-aware synthesis
Incremental synthesis
Interconnect delays

From my perspective, the webinar was not too FPGA oriented as the webinar's title suggested but covered common elements that one will also encounter in ASIC design. I was hoping to learn more about extra features that a third-party EDA vendor might provide that the FPGA providers don't.

At the end, I asked a question about how the TCL scripting commands/arguments. From my point of view, the more there are tools from different vendors in a design flow the more complex is to automate the flow by scripting. Hence I wanted to know more about how the learning curve is when scripting with a third-party synthesis tool for FPGA design. My question was taken as what are the benefits of scripting, but not how difficult would it be for learning different commands/arguments from different vendors which do more or less the same task.

However, I really enjoy the webinar and thank MentorGraphics for their bi-weekly webinars. I am looking forward for the next webinar about CDC (Clock Domain Crossing).

I also participated in their poll. One of the questions on the poll was about which vendor's FPGA I am using. I am always impressed to see in such poll that 2/3 of the participants choose Xilinx's FPGA over Altera's FPGA. I have not yet understood the reason behind it. One of the reasons I would choose Altera's FPGA is because their constraints are in the SDC format, whereas Xilinx uses its own. It reassures me about the certainty of the constraints I want to apply. Hence,this ensures a quicker prototyping for a junior ASIC guy like me who visits the FPGA world.

CDC (Clock Domain Crossing)

Peggy Aycinena interviewed me on opensource EDA, which she published on edadesignline.

Open source EDA software defeats Lock-in—Dream on

Also this week, Ann Rein shared with us that her team is evaluating Fedora Electronic Lab at Universidad Nacional Autonoma de Mexico under 10 machines.

Today, I spent some time to complete my JTAG Controller VHDL design. I started it a few days before Fedora Electronic Lab 11 release.

I was also awaiting the day when someone will talk about a possible merger of Cadence and Magma. Well that news was among my RSS feeds. John Cooley's email about Apache-DA's Techguri blogsite got my attention though. On the other hand, Cadence and Synopsys have paid bloggers.

Last week announced the availability of Fedora 11. This new release entails Windows cross-compilers
introduced by Fedora's MinGW Special Interest Group.

The aim is to eliminate duplication of work for application developers by providing a range of libraries and development tools which have already been ported to the cross-compiler environment. This means that developers will not need to recompile the application stack themselves, but can concentrate just on the changes needed to their own application.

Though this feature will interest a wide range of software developers, I believe EDA vendors will also be very interested. I will demonstrate a quick example of how to use these Windows cross-compilers.

In this demo, I will use gerbv, a gerber viewer and the example "Temperature Collector" developed by Levente Kovacs.

To install gerbv on fedora,

# yum install gerbv

The above screenshot shows gerbv compiled under a normal Linux "configure && make". Now we will compile the same gerbv for Windows.

1. Download the sources of gerbv.

2. Setup your Fedora 11 Linux

# yum install mingw32-gcc mingw32-gtk2 mingw32-crossreport mingw32-nsiswrapper wine

3. Configure Wine.

4. Extract gerbv sources.

5. Compilation of gerbv for Windows
$ cd gerbv-2.2.0
$ mingw32-configure
$ mingw32-make

The final Windows executable file of gerbv will be stored in src/.libs/ as gerbv.exe together with its DLL file, libgerbv-1.dll.

6. Launch gerbv.exe under wine

$ wine src/.libs/gerbv.exe

7. Test gerbv.exe under windows.

Under windows, extra DLLs are required and these can be downloaded from The GTK+ Project or simply from here.

The gerber files used in this example, my compiled gerbv.exe and libgerbv-1.dll can be downloaded from here.

mingw32-nsiswrapper can later be used for building automated Windows installers for distribution.

I hope this short crash course will help you. For any additional details, please join the Fedora Mingw mailing list or IRC: #fedora-mingw on FreeNode.

References:

Fedora IRC Classroom – Using the Windows cross-compiler with Richard Jones
Windows cross compiler Feature wiki page

Last week announced the availability of Fedora 11. This new release entails Windows cross-compilers
introduced by Fedora's MinGW Special Interest Group.

In this demo, I will use gerbv, a gerber viewer and the example "Temperature Collector" developed by Levente Kovacs.

To install gerbv on fedora,

# yum install gerbv

The above screenshot shows gerbv compiled under a normal Linux "configure && make". Now we will compile the same gerbv for Windows.

1. Download the sources of gerbv.

2. Setup your Fedora 11 Linux

# yum install mingw32-gcc mingw32-gtk2 mingw32-crossreport mingw32-nsiswrapper wine

3. Configure Wine.

4. Extract gerbv sources.

5. Compilation of gerbv for Windows
$ cd gerbv-2.2.0
$ mingw32-configure
$ mingw32-make

The final Windows executable file of gerbv will be stored in src/.libs/ as gerbv.exe together with its DLL file, libgerbv-1.dll.

6. Launch gerbv.exe under wine

$ wine src/.libs/gerbv.exe

7. Test gerbv.exe under windows.

mingw32-nsiswrapper can later be used for building automated Windows installers for distribution.

I hope this short crash course will help you. For any additional details, please join the Fedora Mingw mailing list or IRC: #fedora-mingw on FreeNode.

References:

Fedora IRC Classroom – Using the Windows cross-compiler with Richard Jones
Windows cross compiler Feature wiki page

The title of this blog post was copied from Harry Gries's blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior.

Harry's observations are oriented towards the "raw" design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and work hard to satisfy design tools. But in the FPGA environment, the design tools provide an even more automated work flow from frontend to backend. Physical design sometimes (depending on the size of the design) seems to take a few minutes. I have seen people even skip the entire the physical design, unless there is a violation somewhere.

I had a few FPGA projects to handoff and though they were for some different medium-sized companies, sometimes I felt that project managers and reviewers were not serious enough like in ASIC environment. I got a few remarks for my VHDL designs which sometimes coming from a senior FPGA designer shocked me. It is true as well that FPGA design was not their prime development base.

One of those remarks which till now I have not really understood the reason between it and why my reasoning was not valid. It concerned my FSMs. They had "next-state" decoding and "output" decoding into two separate VHDL processes. My reasoning which Altera's appplication notes implies will restrict the synthesis tool from sharing resources with other blocks. The remark I got, during a code review, was "I never seen that in my 12 years career, clean this". I am still eager to know what advantage will my design have while combining these two processes.

I also got the most chaotic code review experience with other FPGA designers. VHDL code review was left incomplete from my point of view and discarded parts of code review with respect to switching rates, power, … due to lack of time. I was expecting a thorough code review for an optimal the sign-off and hand-off like I used to see with ASIC design teams.

I'm sure this is not true in every FPGA design team. What I was to say here is that during the excursion to the FPGA world, the strict discipline routine one has in ASIC environment just fades away. How quickly? I think it depends on the FPGA design team. I could even feel how disconnected the small companies are from the EDA vendors. However, I wish to get myself involved with a "real" high-performance FPGA based design team to see how discipline they are 🙂

While these are issues I personally encountered, I am trying to get Fedora Electronic Lab enough collaborative solutions so that small companies can at least have a decent code review, project hand-off and make FPGA designers happy.

One of the many faces of digital hardware design entails tracking many files to be fed to multiple EDA tools. The eventual reports or netlists are carefully analysed and logged as part of the sign-off methodology. Each company tracks these project dependent files under a certain directory structure and under a certain revision controlled system of their choice.

The development cycle Fedora Electronic Lab 12 has started. One key feature for the next Fedora 12 release will be improving "collaborative hardware development experience" on Fedora. As a test-case scenario, let's imagine 4 persons (from 4 different continents) have encountered each other using a particular social networking medium and want to engage into the development of a FPGA project.

While Fedora Electronic Lab already includes the respective simulators for digital design (VHDL/Verilog), waveforms viewers, schematic editors, PCB layout editor and Fedora's different webserver and security solutions, these 4 persons (test-case scenario) should not have any issue with the latest Fedora 11 release.

For Fedora 12, we want to ensure that these persons have adequate tools to set up a webserver dedicated for hardware design and help them improve their sign-off and code review methodologies. Hardware code review for small inexperienced companies is often misguided and ends up wasting work hours in unnecessary meetings. Designers often have mixed feelings about code reviews. Sometimes when the code review is outsourced to a third party, source codes are sent in the form of tarballs and tracked as tarballs instead of files, which this is no means an efficient way.

We are currently including an efficient and reliable code review solution into the Fedora collection. This free and opensource solution will also help create links and seamless references between bugs, tasks, changesets and files. Project coordinators will have a more realistic the overview of the on-going project and track the progress very easy with respect to different milestones and deadlines.

Coupled with Fedora's commitment in Virtualization and SELinux, hardware designers will benefit with a free and robust platform which can easily be deployed.

Fedora Project – This week announced the availability of Fedora 11 Leonidas and its spins. These spins provide different flavours of Fedora 11 targeting specific users and applications.

The fourth consecutive release of Fedora Electronic Lab is part of those spins, offering the best hardware design and simulation experience with opensource EDA software.

Fedora Electronic Lab 11 Leonidas provides a vibrant environment for designing and simulating ASIC design and embedded design. The opensource EDA solutions are composed to satify high-end mixed-signal hardware design flows from design specification to final project handoff. This release comprises Perl modules to facilitate both design, HDL code generation and brings additional support for Engineering Change Order (ECO). After post chip fabrication, evaluation boards of those chips can also be designed.

Advantages

Deployable in both development and production environments.
No kernel patches are required, making it easy to deploy and use.
No licenses required and it is free.

Key Highlights

Existing RPM packages were updated improve design experience in terms of development time and debugging. The key highlights of the major development items puts the quality barrier higher than the previous releases:

Perl modules to extend vhdl and verilog support. These Perl modules together with gtkwave improves chip testing support.
Perl parsers for VHDL, Verilog and SystemC.
Introduced collaborative development solutions.
Introduction of Verilog-AMS modeling into ngspice.
Improved VHDL debugging support with gcov.
Improved support for re-usable HDL packages as IP core.
Improved PLI support on both iverilog and ghdl
Introduction of C-based methodologies for HDL testbenches and models.
Improved co-simulation based hardware design.
Introduction of design tools for DSP design flow.

Eclipse, the comprehensive Integrated Development Environment (IDE) for embedded systems is also part of the collection. This IDE is included for the first time on the Livedvd (but available since a long time on Fedora repositories) entails plugins for C++, Perl and Version Control systems (CVS,GIT,SVN).

Download the Fedora Electronic Lab 11 flyer for additional details.

Userbase

Students/researchers
Lecturers
Analog/Digital/Mixed Signal hardware designers (even Test engineers)
System Electronic Engineers
Project Coordinators
New opensource EDA developers
Field application engineers

About Fedora Electronic Lab

Fedora Electronic Lab is Fedora's high-end hardware design and simulation platform. This platform provides different hardware design flows based on the semiconductor industry's current trend. FEL maps in new design, simulation and verification methodologies with opensource EDA software.

For more information and download, go to website.

It is with great pleasure that today I've a featured blog on EDACafe. My name is Chitlesh Goorah. I will be exposing different opensource solutions which will interest both EDA engineers and ASIC designers.

Some of you may know me from my work behind Fedora Electronic Lab. For about three years now, we are proposing an opensource ASIC design and simulation platform, which is fairly well accepted by many universities around the world. We are working closely with many upstream projects such as gEDA, veripool, open circuit design, … in order to ensure interoperability between our solutions.

At the same time, Fedora developers are introducing Windows cross-compilers for the next version. Thereby, EDA vendors can also use Fedora or entreprise-class distribution such as RHEL or CentOS as a development ground for their products.

Later, I will introduce other features such as virtualisation, mass deployment, various design handoff checking facilities, … etc each accompanying with at least an example. Many designers and CAD engineers are already using opensource tools such as Vi, Emacs, svn, … I am looking forward to read your comments on my next posts.

I have just pushed dinotrace to Fedora stable repositories. This will elevate the digital design experience for Emacs users.

Fedora users can soon install it with:

# yum install dinotrace emacs-dinotrace

I will briefly describe some features of this co-design possibility which dinotrace and verilog-mode provides on this blog post. However for more technical details, consult the manual.

1: Dinotrace is a waveform viewer which read .vcd files, generated by ghdl or iverilog. It includes a .el file for emacs which enables the designer to interact with the signals on dinotrace via emacs.

To load dinotrace-mode on emacs:
Alt-x dinotrace-mode

To load verilog-mode on emacs:
Alt-x verilog-mode

2: Verilog-mode provides designer with context-sensitive highlighting, auto indenting, and macro expansion capabilities to greatly reduce Verilog coding time. It also prevents additional human errors while coding. I will describe a few macro-expansion capabilities below.

3: Signal highlighting. Both Emacs and dinotrace can share the same colour to represent signals.

4: With annotation feature, the values of the signals with respect to the cursors' position on the waveform viewer is annotated on the Emacs. This will help designers to debug their complex designs efficiently.

The above screenshot shows a simple frequency divider coded with verilog-mode macros and the same verilog after the macros were automatically expanded by Emacs. For more details about other macros, consult the verilog-mode manual. Happy design on Fedora.